1. Field of the Invention
The present invention relates to a method of fabricating a non-volatile memory device and, more particularly, to a method of fabricating a non-volatile memory device having a local SONOS gate structure.
2. Description of the Related Art
Semiconductor memory devices can be classified as volatile memory devices and non-volatile memory devices based on the manner in which data is stored. The volatile memory device loses stored data when the power supply is interrupted, whereas the non-volatile memory device retains data even when the power supply is not supplied thereto. Accordingly, non-volatile memory devices, for example, flash memory devices, are widely employed in mobile communication systems, memory cards, etc.
Non-volatile memory devices can be in turn classified as floating gate type and a charge trap type based on kinds of memory storage layers constituting a unit cell. The floating gate type enjoyed widespread popularity. However, in the floating-gate memory device, charge is stored in polycrystalline silicon, so that memory retention characteristics may be affected by even a small defect in a tunneling oxide layer. On the other hand, a silicon-oxide-nitride-oxide-silicon (SONOS) device which is the charge-trap memory device employing a nitride layer as the memory storage layer has been disclosed in recent years. The SONOS device includes a silicon layer having a channel area formed therein, an oxide layer forming a tunneling layer, a nitride layer used as a charge trapping layer, an oxide layer used as a blocking layer, and a polysilicon layer used as a control gate electrode. The nitride layer is a non-conductive layer, so any charge stored therein do not freely move. Thus, the nitride layer is less affected by a defect in the tunneling oxide layer. As a result, the device has excellent memory retention characteristics. In recent years, a local SONOS gate structure has been proposed where the nitride layer used as the charge trapping layer overlaps only a portion of the control gate electrode. It is well known that the non-volatile memory device having the local SONOS gate structure demonstrates enhanced operating characteristics by adjusting the overlapping length of the charge trapping layer and the control gate electrode.
A method of fabricating the SONOS charge trapping memory device is disclosed in U.S. Pat. No. 6,664,155 B2 entitled “Method of manufacturing semiconductor device with memory area and logic circuit area” to Kasuya et al.
According to Kasuya et al, a gate insulating layer and a first conductive layer are sequentially deposited on the entire surface of a semiconductor substrate having a memory area and a logic circuit area. In addition, a stopper layer is formed on the first conductive layer. The stopper layer and the first conductive layer are patterned to form a word gate on the memory area. An oxide-nitride-oxide (ONO) layer and a control gate are then formed on sidewalls of the word gate. The stopper layer and the first conductive layer are patterned again to form a gate electrode in the logic circuit area.
In general, the SONOS device includes a cell area and a peripheral circuit area. In this case, the cell area substantially indicates the memory area, and the peripheral circuit area substantially indicates the logic circuit area. Low voltage transistors, middle voltage transistors, and high voltage transistors are included in the peripheral circuit area, and cell transistors and select transistors are included in the cell area. In addition, a low voltage or a high voltage is applied to the cell transistor in response to a driving state of the device.
According to the aforementioned conventional approach, however, the thickness of the gate insulating layer that is formed in the cell area and the peripheral circuit area is the same. That is, the cell gate insulating layer and the high voltage gate insulating layer are formed to have the same thickness. When the thickness of the cell gate insulating layer and the high voltage gate insulating layer is small, defects due to stress can be caused in the high voltage transistors. On the contrary, when the thickness of the cell gate insulating layer and the high voltage gate insulating layer is large, the on-cell current of the cell transistor is reduced.
In addition, in the cell transistor of the non-volatile memory device having the local SONOS gate structure, a memory storage pattern and a cell gate insulating layer are simultaneously interposed between a channel area and a control gate electrode. That is, the cell transistor includes the channel area, a memory storage pattern and a cell gate insulating layer planarly disposed on the channel area and having at least one sidewall thereof being in contact with each other, and the control gate electrode covering both of the memory storage pattern and the cell gate insulating layer. In this case, when the cell gate insulating layer is too thick, a problem occurs in that the on-cell current of the cell transistor is reduced.